The present invention relates to a method of wiring in a semiconductor integrated circuit device, and to a method of computer-based automatic wiring in a semiconductor integrated circuit device having four or more wiring layers of signal lines.
A conventional channel wiring method for semiconductor devices is described in publication DA Conference, pp. 298-302, published in 1977. This technique is intended to form signal lines on four wiring layers, and it includes five modes of wiring. The wiring method based on this conventional technique will be explained with reference to the drawings.
FIG. 8 is a diagram showing examples of 4-layer wiring is five wiring modes based on the above-mentioned conventional technique. FIGS. 9 and 10 are diagrams explaining lead wiring from the first layer to the fourth layer. FIGS. 11, 12 and 13 are diagrams explaining the occurrence of undone wiring resulting from the conventional wiring method. In FIGS. 8 through 13, indicated by 1 are terminals, 2 is first layer wiring, 3 is second layer wiring, 4 is third layer wiring, 5 is fourth layer wiring, 6 are through holes, 7 is a row of cells, and 8 are overall through holes.
Generally, a semiconductor integrated circuit device has an internal formation of multiple rows of cells each constituting such a circuit element as a logic gate, with a wiring area in the form of multiple wiring layers being provided between cell rows so that terminals of cells are interconnected in the wiring area thereby to form various functional circuits. Terminals of cells are usually located on the lowest layer and they are led to proper wiring layers for interconnection. In the above-mentioned conventional technique, terminals are connected with each other in any of the wiring modes illustrated in FIG. 8.
Shown by (a) in FIG. 8 is an example of mode-I wiring which is used to connect terminals 1 of adjacent cell rows 7. Lines from both terminals 1 are led to the first layer, resulting lines 2 on the first layer are further led to the second layer by through holes 6, and finally both terminals are interconnected by a line 3 on the second layer.
Shown by (b) and (c) are examples of mode-II wiring and mode-III wiring which are used to connect a terminal 1 of a cell row 7 to a terminal of another cell row (not shown) across intermediate cell rows. For example, a line from a terminal 1 is led to the second layer by a line 2 on the first layer and a through hole 6 and further led to the third layer by a through hole 6, as in the mode-I connection, and finally connected to a terminal of another cell row by a line 4 on third layer.
Shown by (d) and (e) are mode-IV wiring and mode-V wiring which are used for the connection from one cell row by way of a wiring area to another cell row in other portion (not shown). In mode-IV wiring, a line from other portion is led to the wiring area by a line 4 on the third layer, and both lines are connected by a line 3 on the second layer in the wiring area. In mode-V wiring, other line is led to the wiring area by a line 4 on the third layer, and both lines are connected by a line 5 on the fourth layer in the wiring area.
Although the conventional technique is operative for 4-layer wiring in five kinds of wiring mode, it mostly uses lower layers due to the presence of cell terminals on the lowest layer in general, resulting in the inefficient use of the fourth layer. In the examples of FIG. 8, only mode-V wiring can use the fourth layer.
Another problem of the conventional technique, which is due to lead wiring on the first layer for terminals 1, is that when it is intended to connect terminals in mode-V wiring by using a fourth layer line 5, it is necessary to lead the line from a terminal to the third layer by a second layer line 3 and then connected to a third layer line 4 by the fourth layer line 5 as shown in FIG. 9, resulting in the increased wiring on the second and third layers.
In the above-mentioned case, although it is possible to connect the first layer lines of the terminals 1 to the fourth layer line 5 by overall through holes 8 as shown in FIG. 10, the 3-stage through holes (from first to second layer, from second to third layer, and from third to fourth layer) is not desirable from the viewpoints of the structural quality and thus the yield of manufacturing. On this account, lines are routed generally from the lowest layer to the highest layer sequentially by way of intermediate wiring layers. Even in the case of using overall through holes, through holes on the second and third layers can obstruct other wiring, and therefore it is not desirable.
A further problem of the conventional technique, which is due to the determination of the lead wiring route without the assessment of the utilization factors of individual wiring layers, is that when terminals B are connected together by a second layer line 3, it becomes impossible to interconnect terminals A, as shown in FIG. 11. The figure is a plan view of a chip with a wiring area formed between cells, showing the occurrence of undone wiring 11 if lead wiring to a higher layer is not counted in the distribution of each wiring layer in the x direction.
In the example of FIG. 11, a 2-layer pitch 9 and two 4-layer pitches 10 are disposed between cell rows 7, and the second layer line 3 and fourth layer line 5 in the lateral direction can be formed on the layers of this position. When the terminals B are connected together by a second layer line 3, no more second layer wiring is available even through a vacant fourth layer. Consequently, the line from the terminal A cannot be led to the fourth layer by way of the second layer line 3 and third layer line 4 sequentially, and interconnection between terminals A is left as undone wiring 11 unless overall through holes are used.
FIG. 12 shows an example of the case where wiring is made across a cell row based on the conventional technique. Longitudinal lead wiring routes in the y direction for interconnecting terminals C are assigned in excess of 100% of the sum of utilization factors of individual wiring layers in the lateral (x) direction, causing the failure of interconnection between terminals A of the same cell row as undone wiring 11. In the case of this example, if the wiring layer in the x direction is the fourth layer and the wiring layer in the y direction is the first layer for the wiring of interconnection between terminals C, bends of line arise on the second and third layers and the utilization factor of a longitudinal line will exceed 100%.
FIG. 13 shows an example of interconnection between terminals B and between terminals C based on the conventional technique through the assignment of short lines in the x direction to the fourth layer. Leading many short lines to the fourth layer causes increased utilization factors of the second and third layers, resulting in the occurrence of undone wiring 11 for the interconnection between terminals A.